没有合适的资源?快使用搜索试试~ 我知道了~
君正JZ4755完整数据手册
5星 · 超过95%的资源 需积分: 43 89 下载量 75 浏览量
2011-02-15
14:00:16
上传
评论 3
收藏 3.72MB PDF 举报
温馨提示
试读
670页
君正JZ4755完整数据手册Jz4755 Multimedia Application Processor Programming Manual
资源推荐
资源详情
资源评论
Jz4755
Multimedia Application Processor
Programming Manual
Revision: 1.0
Date: May 2009
Jz4755 Multimedia Application Processor
Programming Manual
Copyright © Ingenic Semiconductor Co. Ltd 2007. All rights reserved.
Release history
Date Revision Change
May 2009 1.0 First release
Disclaimer
This documentation is provided for use with Ingenic products. No license to Ingenic property rights is
granted. Ingenic assumes no liability, provides no warranty either expressed or implied relating to
the usage, or intellectual property right infringement except as provided for by Ingenic Terms and
Conditions of Sale.
Ingenic products are not designed for and should not be used in any medical or life sustaining or
supporting equipment.
All information in this document should be treated as preliminary. Ingenic may make changes to this
document without notice. Anyone relying on this documentation should contact Ingenicfor the
current documentation and errata.
Ingenic Semiconductor Co., Ltd.
Room 108, Building A, Information Center, Zhongguancun Software Park
8 Dongbeiwang West Road, Haidian District, Beijing, China,
Tel: 86-10-82826661
Fax: 86-10-82825845
Http: //www.ingenic.cn
CONTENTS
i
CONTENTS
1 Overview............................................................................................ 1
1.1 Block Diagram......................................................................................................................... 2
1.2 Features.................................................................................................................................. 3
1.2.1 Main CPU core ................................................................................................................ 3
1.2.2 Aux CPU core.................................................................................................................. 3
1.2.3 Multimedia support .......................................................................................................... 3
1.2.4 Memory sub-system ........................................................................................................ 3
1.2.5 Clock generation and power management ..................................................................... 4
1.2.6 On-chip peripherals ......................................................................................................... 4
1.3 Characteristic .......................................................................................................................... 8
2 CPU Core .......................................................................................... 9
3 External Memory Controller ..............................................................11
3.1 Overview ................................................................................................................................11
3.2 Pin Description...................................................................................................................... 12
3.3 Physical Address Space Map................................................................................................ 13
3.4 Static Memory Interface ........................................................................................................ 15
3.4.1 Register Description ...................................................................................................... 16
3.4.2 Example of Connection ................................................................................................. 20
3.4.3 Basic Interface............................................................................................................... 23
3.4.4 Byte Control................................................................................................................... 27
3.4.5 Burst ROM Interface...................................................................................................... 30
3.5 NAND Flash Interface ........................................................................................................... 31
3.5.1 Register Description ...................................................................................................... 31
3.5.2 NAND Flash Boot Loader.............................................................................................. 32
3.5.3 NAND Flash Operation.................................................................................................. 33
3.6 SDRAM Interface .................................................................................................................. 35
3.6.1 Register Description ...................................................................................................... 36
3.6.2 Refresh Time Constant Register (RTCOR)................................................................... 44
3.6.3 Example of Connection ................................................................................................. 46
3.6.4 Address Multiplexing ..................................................................................................... 48
3.6.5 SDRAM Command........................................................................................................ 50
3.6.6 SDRAM Timing.............................................................................................................. 51
3.6.7 Power-Down Mode........................................................................................................ 65
3.6.8 Refreshing ..................................................................................................................... 66
3.6.9 Initialize Sequence ........................................................................................................ 70
3.7 Bus Control Register (BCR).................................................................................................. 74
CONTENTS
ii
4 BCH Controller .................................................................................76
4.1 Overview................................................................................................................................76
4.2 Register Description ..............................................................................................................77
4.2.1 BCH Control Register (BHCR).......................................................................................77
4.2.2 BCH Control Set Register (BHCSR)..............................................................................78
4.2.3 BCH Control Clear Register (BHCCR) ..........................................................................78
4.2.4 BCH ENC/DEC Count Register (BHCNT) .....................................................................79
4.2.5 BCH Data Register (BHDR)...........................................................................................80
4.2.6 BH Parity Register (BHPARn, n=0,1,2,3) ......................................................................80
4.2.7 BCH Interrupt Status Register (BHINT) .........................................................................81
4.2.8 BCH Interrupt Enable Set Register (BHINTES).............................................................82
4.2.9 BCH Interrupt Enable Clear Register (BHINTEC) ......................................................... 83
4.2.10 BCH Interrupt Enable Register (BCHINTE)...................................................................84
4.2.11 BCH Error Report Register (BCHERRn, n=0,1,2,3) ......................................................85
4.3 BCH Operation ......................................................................................................................87
4.3.1 Endcoding Sequence.....................................................................................................87
4.3.2 Decoding Sequence ......................................................................................................87
5 DMA Controller .................................................................................89
5.1 Features ................................................................................................................................89
5.2 Register Descriptions ............................................................................................................90
5.2.1 DMA Source Address (DSAn, n = 0 ~ 11)......................................................................92
5.2.2 DMA Target Address (DTAn, n = 0 ~ 11)........................................................................93
5.2.3 DMA Transfer Count (DTCn, n = 0 ~ 11) .......................................................................93
5.2.4 DMA Request Types (DRTn, n = 0 ~ 11) .......................................................................94
5.2.5 DMA Channel Control/Status (DCSn, n = 0 ~ 11)..........................................................95
5.2.6 DMA Channel Command (DCMn, n = 0 ~ 11) ...............................................................96
5.2.7 DMA Descriptor Address (DDAn, n = 0 ~ 11) ................................................................98
5.2.8 DMA Stride Address (DSDn, n = 0 ~ 11)........................................................................99
5.2.9 DMA Control...................................................................................................................99
5.2.10 DMA Interrupt Pending (DIRQP)..................................................................................100
5.2.11 DMA Doorbell (DDR) ...................................................................................................101
5.2.12 DMA Doorbell Set (DDRS)...........................................................................................101
5.2.13 DMA Clock Enable (DCKE) .........................................................................................102
5.3 DMA manipulation ...............................................................................................................103
5.3.1 Descriptor Transfer ......................................................................................................103
5.3.2 No-Descriptor Transfer ................................................................................................107
5.4 DMA Requests.....................................................................................................................108
5.4.1 Auto Request ...............................................................................................................108
5.4.2 On-Chip Peripheral Request........................................................................................108
5.5 DMA Transfer Modes...........................................................................................................108
5.5.1 Single Mode.................................................................................................................108
CONTENTS
iii
5.6 Channel Priorities................................................................................................................ 108
5.7 Examples ............................................................................................................................ 109
5.7.1 Memory-to-memory auto request No-Descriptor Transfer .......................................... 109
6 AHB Bus Arbiter..............................................................................110
6.1 Overview ..............................................................................................................................110
6.2 Register Descriptions...........................................................................................................111
6.2.1 Priority Order Register..................................................................................................111
6.2.2 Monitor Control Register ..............................................................................................112
6.2.3 AHB Clock Counter Low Register ................................................................................113
6.2.4 Event0 Low Register ....................................................................................................113
6.2.5 Event1 Low Register ....................................................................................................114
6.2.6 Event High Register .....................................................................................................114
7 Clock Reset and Power Controller..................................................115
7.1 Overview ..............................................................................................................................115
7.2 Clock Generation UNIT........................................................................................................116
7.2.1 Pin Description .............................................................................................................117
7.2.2 CGU Block Diagram .....................................................................................................118
7.2.3 Clock Overview ............................................................................................................119
7.2.4 CGU Registers ............................................................................................................ 120
7.2.5 PLL Operation ............................................................................................................. 128
7.2.6 Main Clock Division Change Sequence...................................................................... 130
7.2.7 Change Other Clock Frequencies............................................................................... 130
7.2.8 Change Clock Source Selection ................................................................................. 130
7.2.9 EXCLK Oscillator......................................................................................................... 131
7.3 Power Manager................................................................................................................... 132
7.3.1 Low-Power Modes and Function................................................................................. 132
7.3.2 Register Description .................................................................................................... 133
7.3.3 Doze Mode .................................................................................................................. 137
7.3.4 IDLE Mode .................................................................................................................. 137
7.3.5 SLEEP Mode............................................................................................................... 138
7.4 Reset Control Module ......................................................................................................... 138
7.4.1 Register Description .................................................................................................... 138
7.4.2 Power On Reset .......................................................................................................... 139
7.4.3 WDT Reset.................................................................................................................. 139
8 Real Time Clock............................................................................. 140
8.1 Overview ............................................................................................................................. 140
8.1.1 Features ...................................................................................................................... 140
8.1.2 Signal Descriptions...................................................................................................... 140
8.2 Register Description............................................................................................................ 142
8.2.1 RTC Control Register (RTCCR).................................................................................. 143
剩余669页未读,继续阅读
laowai0309
- 粉丝: 0
- 资源: 2
上传资源 快速赚钱
- 我的内容管理 展开
- 我的资源 快来上传第一个资源
- 我的收益 登录查看自己的收益
- 我的积分 登录查看自己的积分
- 我的C币 登录后查看C币余额
- 我的收藏
- 我的下载
- 下载帮助
安全验证
文档复制为VIP权益,开通VIP直接复制
信息提交成功
- 1
- 2
前往页