SystemVerilog Tutorials
The following tutorials will help you to understand some of the new most
important features in SystemVerilog. They also provide a number of code
samples and examples, so that you can get a better “feel” for the
language.
These tutorials assume that you already know some Verilog. If not, you
might like to look at the KnowHow Verilog Designer’s Guide first.
• Data types
• RTL design
• Interfaces
• Clocking
• Assertion-based verification
• Classes
• Testbench automation and constraints
• The Direct Programming Interface (DPI)
SystemVerilog Data Types
This tutorial describes the new data types that Systemverilog introduces. Most of these are
synthesisable, and should make RTL descriptions easier to write and understand.
Integer and Real Types
SystemVerilog introduces several new data types. Many of these will be familiar to C
programmers. The idea is that algorithms modelled in C can more easiliy be converted to
SystemVerilog if the two languages have the same data types.
Verilog’s variable types are
four-state: each bit is 0,1,X or Z. SystemVerilog introduces new
two-state data types, where each bit is 0 or 1 only. You would use these when you do not need X
and Z values, for example in test benches and as for-loop variables. Using two-state variables in
RTL models may enable simulators to be more efficient. Used appropriately, they should not affect
the synthesis results.
Type
Description Example
bit user-defined size bit [3:0] a_nibble;
byte 8 bits, unsigned byte a, b;
shortint 16 bits, signed shortint c, d;
int 32 bits, signed int i,j;
longint 64 bits, signed longint lword;
Two-state integer types
Note that, unlike in C, SystemVerilog specifies the number of bits for the fixed-width types.
Type
Description Example