#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
Uint16 *ExRamStart = (Uint16 *)0x100000;
void EPwmSetup();
void PWM_1ch_UpDwnCnt_CNF(int16 n, int16 period, int16 mode, int16 phase);
void PWM_ComplPairDB_CNF(int16 n, int16 period, int16 mode, int16 phase);
void PWM_ComplPairDB_UpdateDB(int16 n, int16 dbRED, int16 dbFED);
void ADC_SOC_CNF(int ChSel[], int TrigSel[], int ACQPS[], int IntChSel, int mode);
interrupt void SECONDARY_ISR(void); //中断函数
void A0(void); //state A0
void B0(void); //state B0
void C0(void); //state C0
// A branch states
void A1(void); //state A1
void A2(void); //state A2
void A3(void); //state A3
void A4(void); //state A4
// B branch states
void B1(void); //state B1
void B2(void); //state B2
// C branch states
void C1(void);
void C2(void);
void C3(void);
void C4(void);
// Variable declarations
void (*Alpha_State_Ptr)(void); // Base States pointer
void (*A_Task_Ptr)(void); // State pointer A branch
void (*B_Task_Ptr)(void); // State pointer B branch
void (*C_Task_Ptr)(void); // State pointer C branch
// -------------------------------- FRAMEWORK --------------------------------------
int16 VTimer0[4]; // Virtual Timers slaved off CPU Timer 0
int16 VTimer1[4]; // Virtual Timers slaved off CPU Timer 1
int16 VTimer2[4]; // Virtual Timers slaved off CPU Timer 2
//定义变量
volatile long Vin, Vout, Iin, Iout; //四个采样量
#define Vin AdcResult.ADCRESULT1 //
#define Iin AdcResult.ADCRESULT2 //
#define Vout AdcResult.ADCRESULT3 //
#define Iout AdcResult.ADCRESULT4 //
#define PWM_OFF() {EALLOW; EPwm1Regs.TZFRC.bit.OST = 1; EPwm2Regs.TZFRC.bit.OST = 1; EDIS;}
#define PWM_ON() {EALLOW; EPwm1Regs.TZCLR.bit.OST = 1; EPwm2Regs.TZCLR.bit.OST = 1; EDIS;}
#if (CPU_FRQ_150MHZ)
#define ADC_MODCLK 0x3 //高速预定标时钟 HSPCLK = SYSCLK/(2*ADC_MODCLK) = 150/(2*3) = 25MHZ
#endif
#if(CPU_FRQ_100MHZ)
#define ADC_MODCLK 0x2 //=100/(2*2) = 25MHZ
#endif
#define ADC_CKPS 0x0
#define ADC_CPS 0x0
#define ADC_SHCLK 0x1
void main(void)
{
InitSysCtrl();
InitXintf16Gpio(); //zq
EALLOW;
SysCtrlRegs.HISPCP.all = ADC_MODCLK; // HSPCLK = SYSCLKOUT/ADC_MODCLK
EDIS;
DINT;
InitPieCtrl();
// Disable CPU interrupts and clear all CPU interrupt flags:
IER = 0x0000; //不能CPU中断使能寄存器
IFR = 0x0000; //中断标志寄存器
InitPieVectTable();
EALLOW;
PieVectTable.ADCINT = &SECONDARY_ISR;
EDIS;
PieCtrlRegs.PIEIER1.bit.INTx6 = 1; //使能对应的PIE1中断, 由于属于PIE第一组, 因此要使能CPU的INT1
InitAdc();
//设置ADC相关
Alpha_State_Ptr = &A0;
A_Task_Ptr = &A1;
B_Task_Ptr = &B1;
C_Task_Ptr = &C1;
VTimer0[0] = 0;
VTimer1[0] = 0;
VTimer2[0] = 0;
// LedBlinkCnt = 5;
EPwmSetup();
ConfigCpuTimer(&CpuTimer0, 150, 1000);
ConfigCpuTimer(&CpuTimer1, 150, 5000);
ConfigCpuTimer(&CpuTimer2, 150, 20000);
StartCpuTimer0();
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; //ePWM模块基准时钟同步 0 停止, 1 同步
EDIS;
//配置ADC
//时钟频率
AdcRegs.ADCTRL1.bit.CPS = ADC_CPS;
AdcRegs.ADCTRL3.bit.ADCCLKPS = ADC_CKPS;
//采样速率,即脉冲宽度
AdcRegs.ADCTRL1.bit.ACQ_PS = ADC_SHCLK;
//工作方式设置
AdcRegs.ADCTRL1.bit.SEQ_CASC = 1; // 1 Cascaded mode
AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x1;
AdcRegs.ADCTRL1.bit.CONT_RUN = 1; // Setup continuous run
AdcRegs.ADCTRL1.bit.SEQ_OVRD = 1; // Enable Sequencer override feature
AdcRegs.ADCCHSELSEQ1.all = 0x0; // Initialize all ADC channel selects to A0
AdcRegs.ADCMAXCONV.bit.MAX_CONV1 = 0x0; // convert and store in 8 results registers
#define Vfb_outR AdcResult.ADCRESULT1 //
#define IfbR AdcResult.ADCRESULT2 //
#define Vfb_inR AdcResult.ADCRESULT3 //
#define IoutR AdcResult.ADCRESULT4 //
// Channel Selection for Cascaded Sequencer
ChSel[0] = 0; // A0 - O/P Voltage - Dummy
ChSel[1] = 0; // A0 - O/P Voltage
ChSel[2] = 2; // A2 - Transformer Primary Current
ChSel[3] = 9; // B1 - I/P Voltage
ChSel[4] = 12; // B4 - Iout2
TrigSel[0] = 7; // O/P Voltage sampling triggered by EPWM2 SOCA - Dummy
TrigSel[1] = 7; // O/P Voltage sampling triggered by EPWM2 SOCA
TrigSel[2] = 7; // Transformer Primary Current sampling triggered by EPWM2 SOCA
TrigSel[3] = 7; // I/P Voltage sampling triggered by EPWM2 SOCA
TrigSel[4] = 7; // Iout sampling triggered by EPWM2 SOCA
EALLOW;
AdcRegs.SOCPRICTL.bit.SOCPRIORITY = 4; // SOC0-3 are high priority
EDIS;
PWMDRV_PSFB_VMC_SR_CNF(1, PWM_PRD, 1, 1); // ePWM1 and ePWM2, Period=PWM_PRD, SR_Enable=1 (ePWM4), Comp1_Prot=1
ADC_SOC_CNF(ChSel,TrigSel,ACQPS, 16, 0);// ACQPS=8, No ADC channel triggers an interrupt IntChSel > 15,
// Mode= Start/Stop (0)
DPL_Init(); // ASM ISR init
// Lib Module connection to "nets"
//----------------------------------------
// ADC feedback connections
ADCDRV_4ch_RltPtrA = &Adc_Vfbout;
ADCDRV_4ch_RltPtrB = &Adc_Ifb;
ADCDRV_4ch_RltPtrC = &Adc_Vfbin;
ADCDRV_4ch_RltPtrD = &Adc_Iout;
// Connect the PWMDRV_PSFB_VMC_SR driver block
PWMDRV_PSFB_Phase1 = &phase; // Point to the phase net
PWMDRV_PSFB_DbAtoP1 = &dbAtoP_leg; // Point to the left leg dead band adjust
PWMDRV_PSFB_DbPtoA1 = &dbPtoA_leg; // Point to the right leg dead band adjust
//2P2Z connections for the Voltage Loop
CNTL_2P2Z_Ref1 = &VfbSetSlewed; // Slewed Voltage command
CNTL_2P2Z_Out1 = &phase; // Reference command to the current loop
CNTL_2P2Z_Fdbk1 = &Adc_Vfbout; // O/P Voltage feedback
CNTL_2P2Z_Coef1 = &CNTL_2P2Z_CoefStruct1.b2; // point to first coeff.
// Coefficients for the Voltage Loop
// PID coefficients & Clamping (Q26)
Dmax = _IQ24(0.984375);
Pgain = _IQ26(0.001953);
Igain = _IQ26(0.031250);
Dgain = _IQ26(0.0);
// Coefficient init --- Coeeficient values in Q26
// Use IQ Maths to generate floating point values for the CLA
CNTL_2P2Z_CoefStruct1.b2 = Dgain; // B2
CNTL_2P2Z_CoefStruct1.b1 = (Igain-Pgain-Dgain-Dgain); // B1
CNTL_2P2Z_CoefStruct1.b0 = (Pgain + Igain + Dgain); // B0
CNTL_2P2Z_CoefStruct1.a2 = 0.0; // A2 = 0
CNTL_2P2Z_CoefStruct1.a1 = _IQ26(1.0); // A1 = 1
CNTL_2P2Z_CoefStruct1.max = Dmax; //Clamp Hi
CNTL_2P2Z_CoefStruct1.min = _IQ24(0.0); //Clamp Min
Vref = 0;
dbAtoP_leg = 20;
dbPtoA_leg = 18;
#endif // (INCR_BUILD == 2)
//==============================================================================
// Items common to all builds
//==============================================================================
// Configure Comparator1 and DAC for over current protection
DacDrvCnf(1, Ipri_trip, 0, 2, 0); // Comp1, DACval = Ipri_trip, DAC Source is DACval, Ramp Source = don't care, Slope = don't care
EPwm1Regs.TZCLR.bit.OST = 1; // Clear any spurious trips
EPwm2Regs.TZCLR.bit.OST = 1; // Clear any spurious trips
EALLOW;
GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; // 0=GPIO, 1=EPWM1A, 2=Resv, 3=Resv
GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1; // 0=GPIO, 1=EPWM1B, 2=SPISIMO-D, 3=Resv
GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1; // 0=GPIO, 1=EPWM2A, 2=Resv, 3=Resv
GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1; // 0=GPIO, 1=EPWM2B, 2=SPISOMI-D, 3=Resv
GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 1; // 0=GPIO, 1=EPWM4A, 2=SYNCI, 3=SYNCO
GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 1; // 0=GPIO, 1=EPWM4B, 2=SPISTE-D, 3=ECAP2
//All enabled ePWM module clocks are started with the first rising edge of TBCLK aligned
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;
//=================================================================================
// INTERRUPT & ISR INIT
