QNX
®
Neutrino
®
RTOS
System Architecture
For release 6.5.0
© 2010, QNX Software Systems GmbH & Co. KG.
© 1996–2010, QNX Software Systems GmbH & Co. KG. All rights reserved.
Published under license by:
QNX Software Systems Co.
175 Terence Matthews Crescent
Kanata, Ontario
K2M 1W8
Canada
Voice: +1 613 591-0931
Fax: +1 613 591-3579
Email:
info@qnx.com
Web: http://www.qnx.com/
Electronic edition published 2010
QNX, Neutrino, Photon, Photon microGUI, Momentics, Aviage, and related marks, names, and logos are trademarks, registered in certain jurisdictions, of QNX Software
Systems GmbH & Co. KG. and are used under license by QNX Software Systems Co. All other trademarks belong to their respective owners.
Contents
About This Guide xiii
What you’ll find in this guide xv
Typographical conventions xvi
Note to Windows users xvii
Technical support xvii
The Philosophy of QNX Neutrino 11
Design goals 3
An embeddable POSIX OS? 3
Product scaling 3
Why POSIX for embedded systems? 4
Why QNX Neutrino for embedded systems? 5
Microkernel architecture 6
The OS as a team of processes 8
A true kernel 8
System processes 9
Interprocess communication 10
QNX Neutrino as a message-passing operating system 10
Network distribution of kernels 11
Single-computer model 11
Flexible networking 11
The QNX Neutrino Microkernel 132
Introduction 15
The implementation of QNX Neutrino 16
POSIX realtime and thread extensions 16
System services 16
Threads and processes 17
Thread attributes 20
Thread scheduling 24
When are scheduling decisions are made? 24
Scheduling priority 25
Scheduling policies 26
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© 2010, QNX Software Systems GmbH & Co. KG.
IPC issues 31
Thread complexity issues 32
Synchronization services 33
Mutexes: mutual exclusion locks 34
Condvars: condition variables 35
Barriers 36
Sleepon locks 38
Reader/writer locks 39
Semaphores 39
Synchronization via scheduling policy 40
Synchronization via message passing 40
Synchronization via atomic operations 41
Synchronization services implementation 41
Clock and timer services 42
Time correction 43
Timers 43
Interrupt handling 45
Interrupt latency 45
Scheduling latency 46
Nested interrupts 47
Interrupt calls 48
Interprocess Communication (IPC) 533
Synchronous message passing 55
MsgReply() vs MsgError() 58
Message copying 58
Simple messages 60
Channels and connections 61
Pulses 63
Priority inheritance and messages 63
Message-passing API 64
Robust implementations with Send/Receive/Reply 64
Events 66
I/O notification 67
Signals 68
Special signals 70
Summary of signals 71
POSIX message queues 73
Why use POSIX message queues? 73
File-like interface 74
Message-queue functions 74
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© 2010, QNX Software Systems GmbH & Co. KG.
Shared memory 75
Shared memory with message passing 75
Creating a shared-memory object 76
mmap() 77
Initializing allocated memory 81
Typed memory 81
Implementation-defined behavior 82
Practical examples 86
Pipes and FIFOs 87
Pipes 87
FIFOs 88
The Instrumented Microkernel 894
Introduction 91
Instrumentation at a glance 91
Event control 92
Modes of emission 92
Ring buffer 93
Data interpretation 93
System analysis with the IDE 94
Proactive tracing 95
Multicore Processing 975
Introduction 99
Asymmetric multiprocessing (AMP) 99
Symmetric multiprocessing (SMP) 100
Neutrino’s microkernel approach 101
Booting an x86 SMP system 102
Booting a PowerPC or MIPS SMP system 102
How the SMP microkernel works 103
Critical sections 104
Bound multiprocessing (BMP) 105
A viable migration strategy 106
Choosing between AMP, SMP, and BMP 106
Process Manager 1096
Introduction 111
Process management 111
Process primitives 111
Process loading 116
Memory management 116
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