San Francisco State University Nano-Electronics & Computing Research Lab
4. A.1 MODEL OPTIMIZATION....................................................................................................................60
4.A.1.1 Resource Allocation .................................................................................................................60
Figure 4A.b. With resource allocation. ................................................................................................61
4.A.1.2 Flip-flop and Latch optimizations ...........................................................................................64
4.A.1.3 Using Parentheses ...................................................................................................................64
4.A.1.4 Partitioning and structuring the design. ..................................................................................65
4.A.2 OPTIMIZATION USING DESIGN COMPILER ........................................................................................65
4.A.2.1 Top-down hierarchical Compile ..............................................................................................66
4.A.2.2 Optimization Techniques .........................................................................................................67
4. A.3 TIMING ISSUES ................................................................................................................................70
Figure 4A.b Timing diagram for setup and hold On DATA .................................................................70
4.A.3.1 HOW TO FIX TIMING VIOLATIONS .....................................................................................71
Figure 4A.c : Logic with Q2 critical path ............................................................................................73
Figure 4A.d: Logic duplication allowing Q2 to be an independent path. ...........................................73
Figure 4A.e: Multiplexer with late arriving sel signal .........................................................................74
Figure 4A.f: Logic Duplication for balancing the timing between signals .........................................74
Figure 4.A.g : Logic with pipeline stages ............................................................................................74
4A.4 VERILOG SYNTHESIZABLE CONSTRUCTS ..........................................................................................75
5.0 DESIGN VISION ...................................................................................................... 78
5.1 ANALYSIS OF GATE-LEVEL SYNTHESIZED NETLIST USING DESIGN VISION ..................78
Figure 5.a: Design Vision GUI ...........................................................................................................78
Figure 5.b: Schematic View of Synthesized Gray Counter ..................................................................79
Figure 5.c Display Timing Path ...........................................................................................................81
Figure 5.d Histogram of Timing Paths ................................................................................................81
STATIC TIMING ANALYSIS ...................................................................................... 82
6.0 INTRODUCTION ....................................................................................................................................82
6.1 TIMING PATHS .....................................................................................................................................82
6.1.1 Delay Calculation of each timing path: ......................................................................................83
6.2 TIMING EXCEPTIONS ............................................................................................................................83
6.3 SETTING UP CONSTRAINTS TO CALCULATE TIMING:.............................................................................83
6.4 BASIC TIMING DEFINITIONS: ...............................................................................................................84
6.5 CLOCK TREE SYNTHESIS (CTS): .........................................................................................................85
6.6 PRIMETIME TUTORIAL EXAMPLE ..............................................................................................86
6.6.1 Introduction.................................................................................................................................86
6.6.2 PRE-LAYOUT ....................................................................................................................................86
6.6.2.1 PRE-LAYOUT CLOCK SPECIFICATION ..............................................................................87
6.6.3 STEPS FOR PRE-LAYOUT TIMING VALIDATION ...................................................................87
IC COMPILER TUTORIAL ......................................................................................... 92
8.0 BASICS OF PHYSICAL IMPLEMENTATION ..............................................................................................92
8.1 Introduction ...................................................................................................................................92
Figure 8.1.a : ASIC FLOW DIAGRAM ...............................................................................................92
8.2 FLOORPLANNING ................................................................................................................................93
Figure 8.2.a : Floorplan example ........................................................................................................94
8.3 CONCEPT OF FLATTENED VERILOG NETLIST .......................................................................................97
8.3.a Hierarchical Model: ...................................................................................................................97
8.3.b Flattened Model: .........................................................................................................................98
Figure 8.c Floorplanning Flow Chart .................................................................................................98
8.4 PLACEMENT .........................................................................................................................................99
8.5 Routing ........................................................................................................................................100
Figure 8.5.a : Routing grid ................................................................................................................101
8.6 PACKAGING .......................................................................................................................................102
Figure 8.6.a : Wire Bond Example ....................................................................................................102
