Rev. 1.0a High Definition Audio Specification
iii
Contents
1 Introduction .................................................................................................. 16
1.1 Scope and Layout of This Document .......................................................................... 16
1.2 Motivation and Goals .................................................................................................. 16
1.2.1 AC„97 Compatibility ...................................................................................... 17
1.2.2 Feature List .................................................................................................. 17
1.2.3 Related Documents ...................................................................................... 17
2 Architecture Overview ................................................................................. 18
2.1 Hardware System Overview ....................................................................................... 18
2.2 Streams and Channels ............................................................................................... 19
2.3 DMA Channel Operation ............................................................................................ 21
2.4 Initialization and Enumeration ..................................................................................... 22
3 Register Interface ......................................................................................... 24
3.1 Introduction to Controller Registers ............................................................................ 24
3.1.1 Terminology ................................................................................................. 24
3.1.2 General Register Behaviors and Access Requirements ............................... 24
3.1.3 Behavior With 64-bit Addresses ................................................................... 25
3.2 High Definition Audio Controller System Bus Interface Registers ............................... 25
3.3 High Definition Audio Controller Register Set ............................................................. 25
3.3.1 Global Capabilities, Status, and Control ....................................................... 28
3.3.2 Offset 00h: GCAP – Global Capabilities ...................................................... 28
3.3.3 Offset 02h: VMIN – Minor Version ............................................................... 29
3.3.4 Offset 03h: VMAJ – Major Version ............................................................... 29
3.3.5 Offset 04h: OUTPAY – Output Payload Capability ...................................... 29
3.3.6 Offset 06h: INPAY – Input Payload Capability ............................................. 30
3.3.7 Offset 08h: GCTL – Global Control .............................................................. 30
3.3.8 Offset 0Ch: WAKEEN – Wake Enable ......................................................... 31
3.3.9 Offset 0Eh: STATESTS – State Change Status .......................................... 32
3.3.10 Offset 10h: GSTS – Global Status ............................................................... 32
3.3.11 Offset 18h: OUTSTRMPAY – Output Stream Payload Capability ................ 32
3.3.12 Offset 1Ah: INSTRMPAY – Input Stream Payload Capability ...................... 33
3.3.13 Interrupt Status and Control ......................................................................... 33
3.3.14 Offset 20h: INTCTL – Interrupt Control ........................................................ 34
3.3.15 Offset 24h: INTSTS – Interrupt Status .......................................................... 35
3.3.16 Offset 30h: Wall Clock Counter ................................................................... 35
3.3.17 Offset 38h: SSYNC – Stream Synchronization ............................................ 36
3.3.18 Offset 40h: CORB Lower Base Address ...................................................... 36
3.3.19 Offset 44h: CORBUBASE – CORB Upper Base Address ............................. 36
3.3.20 Offset 48h: CORBWP – CORB Write Pointer .............................................. 37
3.3.21 Offset 4Ah: CORBRP – CORB Read Pointer .............................................. 37
3.3.22 Offset 4Ch: CORBCTL – CORB Control ...................................................... 37
3.3.23 Offset 4Dh: CORBSTS – CORB Status ....................................................... 38
3.3.24 Offset 4Eh: CORBSIZE – CORB Size ......................................................... 38
3.3.25 Offset 50h: RIRBLBASE – RIRB Lower Base Address ................................ 39
