FPGA通过IIC协议驱动24LC32（EEPROM）资源-CSDN文库

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24AA32A/24LC32A

Device Selection Table

Features:

• Single-supply with operation down to 1.8V

• Low-power CMOS technology:

- 1 mA active current, typical

-1μA standby current (max.) (I-temp)

• Organized as a single block of 4K bytes (32 Kbit)

• 2-wire serial interface bus, I

C™ compatible

• Cascadable for up to eight devices

• Schmitt Trigger inputs for noise suppression

• Output slope control to eliminate ground bounce

• 100 kHz (<2.5V) and 400 kHz (≥2.5V)

compatibility

• Self-timed write cycle (including auto-erase)

• Page write buffer for up to 32 bytes

• Hardware write-protect for entire memory

• Can be operated as a serial ROM

• Factory programming (QTP) available

• ESD protection > 4,000V

• 1,000,000 erase/write cycles

• Data retention > 200 years

• 8-lead PDIP, SOIC, TSSOP, DFN and MSOP

packages

• Pb-free finish available

• Available temperature ranges:

- Industrial (I): -40°C to +85°C

- Automotive (E): -40°C to +125°C

Description:

The Microchip Technology Inc. 24AA32A/24LC32A

(24XX32A*) is a 32 Kbit Electrically Erasable PROM.

The device is organized as a single block of 4K x 8-bit

memory with a 2-wire serial interface. Low-voltage

design permits operation down to 1.8V, with standby

and active currents of only 1 μA and 1 mA,

respectively. It has been developed for advanced, low-

power applications such as personal communications

or data acquisition. The 24XX32A also has a page write

capability for up to 32 bytes of data. Functional address

lines allow up to eight devices on the same bus, for up

to 256 Kbits address space. The 24XX32A is available

in the standard 8-pin PDIP, surface mount SOIC,

TSSOP, 2x3 DFN and MSOP packages.

Package Types

Block Diagram

Part

Number

VCC

Range

Max. Clock

Frequency

Temp.

Ranges

24AA32A 1.8-5.5 400 kHz

(1)

24LC32A 2.5-5.5 400 kHz I, E

Note 1: 100 kHz for VCC <2.5V

Vcc

SCL

SDA

Vss

VCC

SCL

SDA

PDIP, MSOP

SOIC, TSSOP

SCL

SDA

DFN

SCL

SDA

ROTATED TSSOP

HV Generator

EEPROM

Array

Page Latches

YDEC

XDEC

Sense Amp.

R/W Control

I/O

Control

Logic

I/O

Memory

Control

Logic

SCL

SDA

Vcc

32K I

™

Serial EEPROM

*24XX32A is used in this document as a generic part

number for the 24AA32A/24LC32A devices.

24AA32A/24LC32A

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

(†)

VCC.............................................................................................................................................................................6.5V

All inputs and outputs w.r.t. V

SS ......................................................................................................... -0.3V to VCC +1.0V

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temperature with power applied................................................................................................-40°C to +125°C

ESD protection on all pins ......................................................................................................................................................≥ 4kV

TABLE 1-1: DC CHARACTERISTICS

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only and functional operation of the device at those or any other conditions

above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating

conditions for extended periods may affect device reliability.

DC CHARACTERISTICS

Industrial (I): TA = -40°C to +85°C, VCC = +1.8V to +5.5V

Automotive (E): T

A = -40°C to +125°C, VCC = +2.5V to +5.5V

Param.

No.

Symbol Characteristic Min. Typ. Max. Units Conditions

D1 — A0, A1, A2, WP, SCL

and SDA pins

— ————

D2 V

IH High-level input voltage 0.7 VCC ——V—

D3 VIL Low-level input voltage — — 0.3 VCC

0.2 VCC

VCC ≥ 2.5V

CC < 2.5V

D4 VHYS Hysteresis of Schmitt

Trigger inputs (SDA,

SCL pins)

0.05 VCC ——VVCC ≥ 2.5V (Note 1)

D5 VOL Low-level output voltage — — 0.40 V IOL = 3.0 mA, VCC = 4.5V

OL = 2.1 mA, Vcc = 2.5V

D6 I

LI Input leakage current ——±1μAVIN = VSS or VCC, WP = VSS

VIN = VSS or VCC, WP = VCC

D7 ILO Output leakage current ——±1μAVOUT = VSS or VCC

D8 CIN,

OUT

Pin capacitance

(all inputs/outputs)

——10pFVCC = 5.0V (Note 1)

A = 25°C, FCLK = 1 MHz

D9 ICC write Operating current —0.1 3mAVCC = 5.5V, SCL = 400 kHz

D10 I

CC read — 0.05 400 μA

D11 ICCS Standby current —

—

0.01

—

μA

Industrial

Automotive

SDA = SCL = VCC = 5.5V

A0, A1, A2, WP = V

Note 1: This parameter is periodically sampled and not 100% tested.

2: Typical measurements taken at room temperature.

24AA32A/24LC32A

TABLE 1-2: AC CHARACTERISTICS

AC CHARACTERISTICS

Industrial (I): TA = -40°C to +85°C, VCC = +1.8V to +5.5V

Automotive (E): T

A = -40°C to +125°C, VCC = +2.5V to +5.5V

Param.

No.

Symbol Characteristic Min. Max. Units Conditions

CLK Clock Frequency —

—

400

100

kHz 2.5V ≤ VCC ≤ 5.5V

1.8V ≤ V

CC < 2.5V (24AA32A)

2 THIGH Clock High Time 600

4000

—

ns 2.5V ≤ VCC ≤ 5.5V

1.8V ≤ V

CC < 2.5V (24AA32A)

LOW Clock Low Time 1300

4700

—

ns 2.5V ≤ VCC ≤ 5.5V

1.8V ≤ V

CC < 2.5V (24AA32A)

4TR SDA and SCL Rise Time

(Note 1)

—

300

1000

ns 2.5V ≤ VCC ≤ 5.5V

1.8V ≤ V

CC < 2.5V (24AA32A)

5TF SDA and SCL Fall Time — 300 ns (Note 1)

6THD:STA Start Condition Hold Time 600

4000

—

ns 2.5V ≤ VCC ≤ 5.5V

1.8V ≤ V

CC < 2.5V (24AA32A)

7TSU:STA Start Condition Setup Time 600

4700

—

ns 2.5V ≤ VCC ≤ 5.5V

1.8V ≤ V

CC < 2.5V (24AA32A)

HD:DAT Data Input Hold Time 0 — ns (Note 2)

9TSU:DAT Data Input Setup Time 100

250

—

ns 2.5V ≤ VCC ≤ 5.5V

1.8V ≤ V

CC < 2.5V (24AA32A)

10 T

SU:STO Stop Condition Setup Time 600

4000

—

ns 2.5V ≤ VCC ≤ 5.5V

1.8V ≤ V

CC < 2.5V (24AA32A)

11 TSU:WP WP Setup Time 600

4000

—

ns 2.5V ≤ VCC ≤ 5.5V

1.8V ≤ V

CC < 2.5V (24AA32A)

12 THD:WP WP Hold Time 1300

4700

—

ns 2.5V ≤ VCC ≤ 5.5V

1.8V ≤ V

CC < 2.5V (24AA32A)

13 T

AA Output Valid from Clock

(Note 2)

—

900

3500

ns 2.5V ≤ VCC ≤ 5.5V

1.8V ≤ V

CC < 2.5V (24AA32A)

14 TBUF Bus free time: Time the bus

must be free before a new

transmission can start

1300

4700

—

ns 2.5V ≤ VCC ≤ 5.5V

1.8V ≤ V

CC < 2.5V (24AA32A)

15 T

OF Output Fall Time from VIH

Minimum to V

IL Maximum

20+0.1C

—

250

ns 2.5V ≤ V

CC ≤ 5.5V

1.8V ≤ V

CC < 2.5V (24AA32A)

16 TSP Input Filter Spike Suppression

(SDA and SCL pins)

—50ns(Notes 1 and 3)

17 T

WC Write Cycle Time (byte or

page)

—5ms—

18 — Endurance 1M — cycles 25°C, (Note 4)

Note 1: Not 100% tested. C

B = total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

3: The combined T

SP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved

noise spike suppression. This eliminates the need for a

TI specification for standard operation.

4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific

application, please consult the Total Endurance™ Model which can be obtained on Microchip’s web site at

www.microchip.com.

24AA32A/24LC32A

FIGURE 1-1: BUS TIMING DATA

(unprotected)

(protected)

SCL

SDA

OUT

24AA32A/24LC32A

2.0 FUNCTIONAL DESCRIPTION

The 24XX32A supports a bidirectional, 2-wire bus and

data transmission protocol. A device that sends data

onto the bus is defined as transmitter, while a device

receiving data is defined as a receiver. The bus has to

be controlled by a master device which generates the

Serial Clock (SCL), controls the bus access and gener-

ates the Start and Stop conditions, while the 24XX32A

works as slave. Both master and slave can operate as

transmitter or receiver, but the master device

determines which mode is activated.

3.0 BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is high. Changes in

the data line while the clock line is high will be

interpreted as a Start or Stop condition.

Accordingly, the following bus conditions have been

defined (Figure 3-1).

3.1 Bus Not Busy (A)

Both data and clock lines remain high.

3.2 Start Data Transfer (B)

A high-to-low transition of the SDA line while the clock

(SCL) is high determines a Start condition. All

commands must be preceded by a Start condition.

3.3 Stop Data Transfer (C)

A low-to-high transition of the SDA line while the clock

(SCL) is high determines a Stop condition. All

operations must be ended with a Stop condition.

3.4 Data Valid (D)

The state of the data line represents valid data when,

after a Start condition, the data line is stable for the

duration of the high period of the clock signal.

The data on the line must be changed during the low

period of the clock signal. There is one clock pulse per

bit of data.

Each data transfer is initiated with a Start condition and

terminated with a Stop condition. The number of data

bytes transferred between Start and Stop conditions is

determined by the master device and is, theoretically,

unlimited (although only the last thirty two bytes will be

stored when doing a write operation). When an over-

write does occur, it will replace data in a first-in first-out

(FIFO) fashion.

3.5 Acknowledge

Each receiving device, when addressed, is obliged to

generate an acknowledge after the reception of each

byte. The master device must generate an extra clock

pulse which is associated with this Acknowledge bit.

The device that acknowledges, has to pull down the

SDA line during the Acknowledge clock pulse in such a

way that the SDA line is stable low during the high

period of the acknowledge related clock pulse. Of

course, setup and hold times must be taken into

account. During reads, a master must signal an end of

data to the slave by not generating an Acknowledge bit

on the last byte that has been clocked out of the slave.

In this case, the slave (24XX32A) will leave the data

line high to enable the master to generate the Stop

condition.

FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

Note: The 24XX32A does not generate any

Acknowledge bits if an internal

programming cycle is in progress.

SCL

SDA

(A) (B) (D) (D) (A)(C)

Start

Condition

Address or

Acknowledge

Valid

Data

Allowed

to Change

Stop

Condition

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