Preface
A video signal is represented as a sequence of frames of pixels. There exists vast
amount of redundant information that can be eliminated with video compression
technology so that its transmission and storage becomes more efficient. To facilitate
interoperability between compression at the video producing source and decompres-
sion at the consumption end, several generations of video coding standards have
been defined and adapted.
After MPEG-1 for VCD and MPEG-2 for DVD applications, H.264/AVC is
the latest and most advanced video coding standard defined by the international
standard organizations. Its high compression ratio comes at the expense of more
computational-intensive coding algorithms. For low-end applications, software so-
lutions are adequate. For high-end applications, dedicated hardware solutions are
needed.
This book describes an academic project of developing an application-specific
VLSI architecture for H.264/AVC video encoding. Each subfunction is analyzed
before a suitable parallel-processing architecture is designed. Integration of sub-
functional modules as well as the integration into a bus-based SOC platform is
presented. The whole encoder has been prototyped using an FPGA.
Intended readers are researchers, educators, and developers in video coding sys-
tems, hardware accelerators for image/video processing, and high-level synthesis
of VLSI. Especially, those who are interested in state-of-the-art parallel architecture
and implementation of intra prediction, integer motion estimation, fractional motion
estimation, discrete cosine transform, context-adaptive binary arithmetic coding,
and deblocking filter will find design ideas from this book.
HsinChu, Taiwan, ROC Youn-Long Lin
Chao-Yang Kao
Huang-Chih Kuo
Jian-Wen Chen
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