WM8805 中文

DEVICE DESCRIPTION 设备描述

INTRODUCTION 介绍

FEATURES 特性

IEC-60958-3 compatible with 32 to 192k frames/s support.

•支持 IEC-60958-3 兼容 32 到 192 k 帧/ s。

Supports AES-3 data frames.

支持 AES-3 数据帧。

Dedicated high drive clock output pin.

专用高驱动时钟输出引脚。

Register controlled channel status bit configuration.

寄存器控制通道状态位配置。

Register read-back of recovered channel status bits and error flags.

寄存器中断查询通道状态位和错误标志。

Detection of non-audio data, sample rate and de-emphasis.

检测非音频数据,采样率和去加重。

Programmable GPOs for error flags and frame status flags.

•可编程 GPOs 错误旗帜和帧状态标志。

the digital audio interface or, alternatively, the device can loop the received S/PDIF data back out through

the S/PDIF transmitter producing a de-jittered S/PDIF transmit data stream. The recovered clock may be

routed to a high drive output pin for external use. If there is no S/PDIF input data stream the PLL can be

configured to output all standard MCLK frequencies or it can be configured to maintain the frequency of

the last received S/PDIF data stream.

接收器处理数据和时钟恢复,并且通过芯片数字音频接口传输恢复的数据要么

,或者设备可以循环接收的S / PDIF数据回收S / PDIF发射机产生一个S / PDIF

低抖动传输数据流。恢复的时钟可能被发送到一个高驱动输出引线外用。如果没有

S / PDIF输入数据流，这个锁相环可以被配置为去维持最后一次收到的 S / PDIF数据 流的

频率。

S/PDIF is a serial, bi-phase-mark encoded data stream. An S/PDIF frame consists of two sub-frames.

Each sub-frame is made up of:

S / PDIF是串行,双相标记编码数据流。一个S / PDIF帧包括两个子帧。每个子帧 是

由构成:

Preamble – a synchronization pattern used to identify the s tart of a 192-frame block or sub-

frame

•序文——一个同步模式用来识别 192 -帧块或付帧的标志

4-bit Auxiliary Data (AUX) – ordered LSB to MSB

•4 位辅助数据(辅助)——顺序为 MSB 到 LSB

20-bit Audio Data (24-bit when combined with AUX) – ordered LSB to MSB

通道位——超过 192——帧,这形成一个通道状态块

Parity Bit – used to maintain even parity over the sub-frame (not including the preamble)

校验位——用于维持甚至奇偶校验在付帧内(不包括序言)

An S/PDIF Block consists of 192 frames. Channel and user blocks are incorporated within the 192-frame

S/PDIF Block. For Cons umer mode only the first 40-frames are used to make up the Channel and User

blocks. Figure 6 illustrates the S/PDIF format. The WM8805 does not support transmission of user channel

data. Received user channel data may be accessed via GPO pins.

一个S / PDIF块由192帧组成。通道和用户块结合在一起在S / PDIF 192帧块之内。对于缺点欧麦尔模式只有第一个40

帧用来携带通道和用户模块。图6演示了S / PDIF格式。这个WM8805不支持用户数据传输通道。收到用户信道数据可以通

过GPO脚进入。

Note: AIF_CONF[1:0] configures the audio interface when the device operates in hardware mode.

Refer to Table 16 for description of modes.

Table 6 Device Configuration at Power up or Hardware Reset

注意 :当 设备运 行在

硬 件 模 式

AIF_CONF[1:0]配置音

频接口。

参考表16描述模式。

表 6 设备配置在上电

或硬件复位

当设备上电时,所有的上电配置脚被配置为输入在最低9.4us和最高25.6us时跟随外部复位。时间

基准是分别建立在27 mhz和10 mhz晶体时钟频率上。这使得这些脚被取样和设备被配置之前释

放它们选定的操作条件。图7说明了SDIN如何取样。

If the

devic

e is

power

ed up

in

Softw

l mode, all functions of the device are powered

down by default and must be powered up

individually by writing to the relevant bits of the

PWRDN register (table 7). In Hardware Control

Mode, all functions of the device are powered up

by default.

INTERFACE

OPERATION 控制

界面操作

Control of the WM8805 is implemented in either hardware control mode or software control mode. The

method of control is determined by sampling the state of the SDIN/HWMODE pin at power up or at a

hardware reset. If SDIN/HWMODE is low during power up the device is configured in hardware control

mode, otherwise the device is configured in software control mode.

WM8805控制的实现无论是硬件控制模式或软件控制方式。该控制方法是在电源上电或硬件复位时由HWMODE/SDIN

脚采样状态所决定。如果在上电期间SDIN / HWMODE是低设备被配置在硬件控制模式,否则设备配置为在软件控制方式。

Software control is achieved using a 3-wire (3-wire write, 4-wire read) or a 2-wire serial interface.

软件控制是通过使用一个 3 线(3 线写四读)或一个 2 线串行接口。

3线(SPI兼容)串行控制模式——寄存器写

SDIN is used for the program data, SCLK is used to clock in the program data and CSB is used to latch in

the program data. SDIN is sampled on the rising edge of SCLK. The 3-wire interface write protocol is shown

in Figure 8.

SDIN用于程序数据,SCLK用于时钟程序中的数据和CSB 是用来锁住的程序数据。SDIN是在SCLK前沿采样的。3线接口

的编写协议如图8所示。

can be read. These status registers are labelled as “read only” in the Register Map section.

The read-only status registers can be read back via the SDOUT pin. The registers can be read by one of

two methods, selected by the CONT register bit and the ‘W’ control bit. The oscillator must be powered up

before 3-wire control interface read-back is possible.

When CONT =1 and ‘W’=0, a single read-only register can be read back by writing to any other register

or to a dummy register. The register to be read is determined by the READMUX[2:0] bits.

When a write to the device is performed, the device will respond by returning the status byte of the register

selected by the READMUX register bits. The data is returned on the SDOUT pin. This 3-wire interface read-

back method using a write acces s is shown in Figure 9.

并不是所有的寄存器可以被阅读。只有设备ID(寄存器R0、R1和R2)和状态寄存器可以

The second method of reading the read only status registers is If CONT=0 and ‘W’=1. Using this method

devices on the 2-wire bus will shift in the next eight bits on SDIN (7-bit address DEVA(7:1), +