1.1 FEATURES
Memory configuration Four 8-bit timer. (T0, TC0, TC1, TC2).
Flash ROM size: 6K x 16 bits. Including EEROM T0: Basic timer.
emulation. (In system programming) TC0: Timer/counter/PWM0.
RAM size: 512 x 8 bits. TC1: Timer/counter/PWM1.
8 levels stack buffer. TC2: Timer/counter/PWM2
13 interrupt sources 3 channel duty/cycle programmable PWM to
11 internal interrupts: T0, TC0, TC1, TC2, T1, ADC, Generate PWM, Buzzer and IR carrier signals.
SIO, MSP, UTX(UART TX), URX(UART RX), WAKE (PWM0~2).
2 external interrupts: INT0, INT1 One 16-bit timer (T1) with capture timer function.
Multi-interrupt vector structure. 12- channel 10-bit SAR ADC.
Each of interrupt sources has a unique interrupt vector. Serial Interface: SIO, UART, MSP
Build in Embedded ICE function.
I/O pin configuration
Bi-directional: P0, P1, P4, P5. Four system clocks
Wakeup: P0, P1 level change. External high clock: RC type up to 10MHz
Pull-up resisters: P0, P1, P4, P5. External high clock: Crystal type up to 16MHz
External interrupt: P0.0, P0.1 Internal high clock: RC type 16MHz
ADC input pin: AIN0~AIN11. Internal low clock: RC type 16KHz
Four operating modes
Fcpu (Instruction cycle) Normal mode: Both high and low clock active
Fcpu = Fhosc/1, Fhosc/2, Fhosc/4, Fhosc/8, Fhosc/16, Slow mode: Low clock only
Fhosc/32, Fhosc/64, Fhosc/128 Sleep mode: Both high and low clock stop
On chip watchdog timer and clock source Green mode: Periodical wakeup by timer
1.8V/2.4V/3.3V 3-level LVD with trim. Package (Chip form support)
PDIP 32 pin
Powerful instructions LQFP 32 pin
Instruction’s length is one word. QFN 32 pin
Most of instructions are one cycle only. SKDIP 28 pin
All ROM area JMP instruction. SOP 28 pin
All ROM area lookup table function (MOVC). SSOP 28 pin
QFN 28 pin
DIP 20 pin
SOP 20 pin
