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© 2005, Cisco Systems, Inc. All rights reserved.
RTG-HSD-DAC 2005
Things You Can Learn From
An IBIS Model
CDNLive 2005 / Silicon Valley
Todd Westerhoff
Cisco Systems, Inc.
© 2005, Cisco Systems, Inc. All rights reserved.
2
CDNLive 2005, Silicon ValleyThings in an IBIS model
IBIS Models
• Normally used only for simulation purposes
- Signal quality analysis – “clean waveforms”
- Flight time analysis – static timing closure
© 2005, Cisco Systems, Inc. All rights reserved.
3
CDNLive 2005, Silicon ValleyThings in an IBIS model
IBIS Models
• Can also be used for design decisions:
- At what length does a PCB trace become “distributed”?
- How strong is the driver?
- What termination scheme / value should be used?
- Should PCB traces compensate for package skew?
• IBIS models can provide insight into model quality and
simulation results:
- Is the package model good enough?
- What happens if we have poor signal quality at an input
pin?
© 2005, Cisco Systems, Inc. All rights reserved.
4
CDNLive 2005, Silicon ValleyThings in an IBIS model
Distributed Traces – Rule of Thumb
“When the signal rise time is less than 3X
the round-trip delay of the PCB trace, the
trace should be treated as distributed”
© 2005, Cisco Systems, Inc. All rights reserved.
5
CDNLive 2005, Silicon ValleyThings in an IBIS model
Rise/Fall Times and IBIS Models
The IBIS model lists rise/fall time data for
each buffer in the model
[Model] LVTTL16F
Model_type I/O
Polarity Non-Inverting
Enable Active-Low
.
.
.
[Ramp]
| variable typ min max
dV/dt_r 1.29/0.44n 1.04/0.60n 1.52/0.34n
dV/dt_f 1.44/0.46n 1.16/0.64n 1.65/0.35n
R_load = 50.00
IBIS Model File
The [Ramp] keyword
in an IBIS model lists
the 20-80% rise and
fall times for the buffer
In this case, the
rise/fall time is
approximately 450 ps
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