用7段共阳数码管显示任意一个4位数的verilog程序

module Test7Seg(sys_clk,rst_n,seg_dat,seg_sl);
input sys_clk;
input rst_n;
output [7:0] seg_dat;        //the data  
output [3:0] seg_sl;         //choose the seg
parameter N=5678;            //N is the number that are going to display
reg [3:0] seg_sl;
reg [7:0] seg_dat;
reg[15:0] count;
reg clk_1k;

always@(posedge sys_clk or negedge rst_n)
begin
if(!rst_n)
count<=16'd0;
else if(count==16'd50000)
begin
count<=0;
clk_1k<=~clk_1k;
end
else
count<=count+1;
end

reg[3:0] N1,N2,N3,N4;
reg [7:0] reg_a[9:0];
initial 
begin
         reg_a[0] <= 8'hc0;